Applications and advantages of a set/reset latch circuit are well known. For example, latch circuits may be used to implement timing and control functions or to store outputs which are to be delayed. In some applications, an edge set/reset latch circuit may be more useful than a level sensitive set/reset latch circuit which functions in response to a predetermined signal level rather than in response to the transition of a signal edge. The output of an edge set/reset latch circuit will respond to a first input signal applied to a first input thereof as the first input signal becomes active even if a second input signal applied to a second input of the latch circuit is at a logic high level (i.e. active). In contrast, a level sensitive set/reset latch circuit typically defaults to a standby condition if signals at both inputs of the latch circuit become active during the same time period.
Edge sensitive set/reset latch circuits have been implemented with three memory storage circuits, such as three D-type flip flop circuits, and some additional logic circuitry. As a result, an edge sensitive set/reset latch circuit is typically much larger in size than a level sensitive set/reset latch circuit. In applications which require a plurality of set/reset latch circuits, edge sensitive set/reset latch circuits usually require too much circuit size so that a level sensitive set/reset latch circuit with less desirable circuit characteristics must be used.